A thin film transistor liquid crystal display (TFT-LCD) comprises an array substrate and a color filter substrate cell-assembled with liquid crystal interposed therebetween. The array substrate is formed with gate lines, data lines and a plurality of pixel units arranged in a matrix, and each pixel unit is provided with a thin film transistor, a pixel electrode and so on.
For example, FIG. 1 is a cross-sectional structural view of the array substrate obtained during various steps according to a conventional manufacturing method of the array substrate. As shown in FIG. 1, the conventional manufacturing method of the array substrate comprises:
Step S101: a gate electrode 1 and a gate line 2 are formed. A gate metal material layer is deposited on a base substrate, and the gate electrode 1 and the gate line 2 are formed through a patterning process using a mask, as illustrated in FIG. 1A.
Step S102: a gate insulating layer 3 and an active layer 4 are formed. An insulating material layer is deposited above the gate electrode 1 and the gate line 2 to form the gate insulating layer 3; a semiconductor layer is deposited on the gate insulating layer 3; and the active layer 4 disposed above the gate electrode 1 is formed through a patterning process using a mask, as illustrated in FIG. 1B.
Step S103: a pixel electrode 6 is formed. A transparent conductive film is deposited above the active layer 4 and the transparent conductive film is patterned through a patterning process using a mask to form the pixel electrode 6, as illustrated in FIG. 1C.
Step S104: a gate insulating layer via hole 9 electrically connecting the gate line and a signal line is formed. Through a patterning process using a mask, the gate insulating layer via hole 9 is formed at a position of the gate insulating layer 3 corresponding to the signal line to be formed, so that the subsequently-formed signal line is electrically connected to the gate line 2 through the gate insulating layer via hole 9, as illustrated in FIG. 1D.
Step S105: a metal layer is deposited to form the signal line 5, a source electrode 51 and a drain electrode 52. The metal layer is deposited above the gate insulating layer with the gate insulating layer via hole 9 formed therein; the source electrode 51 and the drain electrode 52 disposed above the gate electrode 1 and the active layer 4 are formed through a patterning process using a mask; the drain electrode 52 is connected to the pixel electrode 6; at the same time when the source/drain electrodes are formed, the signal line 5 disposed above the gate line 2 is also formed; and the signal line 5 is electrically connected to the gate line 2 through the gate insulating layer via hole 9, as illustrated in FIG. 1E.
Step S106: a passivation layer 7 is formed on the source/drain electrodes, and the passivation layer 7 is patterned through a patterning process using a mask to form a passivation layer via hole 10 that is used for an electric connection between a common electrode and the signal line, as illustrated in FIG. 1F.
Step S107: a common electrode layer is deposited on the passivation layer 7 and patterned through a patterning process using a mask to form the common electrode 8, and the common electrode 8 is electrically connected to the signal line 5 through the passivation layer via hole 10, so that the gate line 2, the signal line 5 and the common electrode 8 are electrically connected to each other, as illustrated in FIG. 1G.
Herein, the patterning process using a mask comprises coating a photoresist, exposing the photoresist using the mask, developing, etching, removing the photoresist and the like.
In the above-mentioned conventional manufacturing method of the array substrate, a via hole is formed in a gate insulating layer, then a metal layer is deposited, so that an electric connection between the gate line and the signal line is realized, and then the patterning processes for source/drain electrodes, a passivation layer and the like are performed, so it is required to use masks seven times to perform the patterning processes, but the excessive use of the masks affects the producing efficiency greatly, so that the cost is increased, the process is more complicated and the yield is further reduced.